This invention relates generally to processing within a computing environment, and more particularly to a memory ordered store system that provides for speculative stores.
In a computing system within a Peripheral Component Interconnect Express (PCIe) environment, ordering rules ensure a uniformity to provide memory consistency. For example, when an input/output (I/O) adapter writes into system memory, using PCIe defined Posted Memory Write Requests, the updates in memory appear in order to the system software or device driver. In a typical I/O operation, an adapter writes a block of data followed by status into system memory. This operation usually requires several Posted Memory Write Requests and these requests must appear to the system software to be written in strict order in system memory. Therefore, if the system software polls the status waiting for a completion, it knows that any associated data previously written in system memory is valid. Interrupts from I/O adapters are called MSIs (Message Signaled Interrupts) and appear as Posted Memory Write Requests on the PCI interface. Because interrupts are Posted Memory Write Requests, they are also ordered with respect to other Posted Memory Write Requests and the other ordering rules described below. When the program receives an interrupt from an I/O adapter, it knows that all data and status information has been written in to memory and is valid.
Another ordering rule ensures that when an adapter writes data into system memory and then fetches data from the same system memory address, it observes the new data just written. Still another ordering rule ensures that when software reads data, perhaps just a single register in an adapter, when the read response is received by the software it knows that any previous Posted Memory Write data is visible in system memory. This rule is useful in synchronizing operation between the adapter and software.
The rate at which the I/O adapter may write to memory is limited by ordering rules that limit when a subsequent write may be launched. These rules ensure that that the resulting Posted Memory Write data is not seen by the software as being out of order. One rule sometimes referred to, as “strict serialization,” does not allow a subsequent write to be launched until a final write response is received confirming the successful store to memory of the data at the desired address. If no error occurred in the first store to memory, the subsequent store to memory may be launched once the final write response is received. While strict serialization ensures that the stores to memory will be viewed in order, this process may be slower than desired due since only one store to memory may be written at a time. A second rule, sometimes referred to as “partially overlapped ordered stores” provides for the launching of a second store to memory once a coherency response is received from a first store to memory. The second store to memory will proceed unless the first store to memory ends in an error, in which case the second store to memory is cancelled. The partially overlapped ordered stores is useful in increasing the storage rate provided that the number of errors is within desired limits.
In some computer systems, including System z® servers offered by International Business Machines Corporation, implement higher performance I/O interfaces that have performance requirements for the ordered stores that can not be met by strict serialization or partially overlapped rules. For strict serialization systems, the rate at which stores to memory may be achieved is limited by time it takes to receive a final response. For partially overlapped systems, the rate at which stores to memory may be achieved is limited by the time is takes to receive a coherency response.